module ShiftRegister(
  input logic clk,
  input logic reset,
  output logic [7:0] leds
);
  logic [7:0] shift_reg;

  always_ff @(posedge clk or posedge reset) begin
    if (reset)
      shift_reg <= 8'b00000001;
    else
      shift_reg <= {shift_reg[6:0], shift_reg[7]};
  end

  assign leds = shift_reg;

endmodule